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? 2014 microchip technology inc. ds20005271b-page 1 34aa04 device selection table features 4 kbit eeprom: - internally organized as two 256 x 8-bit banks - byte or page writes (up to 16 bytes) - byte or sequential reads within a single bank - self-timed write cycle (5 ms max.) jedec ? jc42.4 (ee1004-v) serial presence detect (spd) compliant for dram (ddr4) modules high-speed i 2 c? interface: - industry standard 1 mhz, 400 khz, and 100 khz - schmitt trigger inputs for noise suppression - smbus-compatible bus time out - cascadable up to eight devices write protection: - reversible software write protection for four individual 128-byte blocks low-power cmos technology: - voltage range: 1.7v to 3.6v - write current: 1.5 ma at 3.6v - read current: 200 a at 3.6v, 400 khz - standby current: 1 a at 3.6v high reliability: - more than one million erase/write cycles - data retention: > 200 years - esd protection: > 4000v 8-lead pdip, soic, tssop, tdfn, and udfn packages available temperature ranges: - industrial (i): -40c to +85c - automotive (e): -40c to +125c description the microchip technology inc. 34aa04 is a 4 kbit electrically erasable prom which utilizes the i 2 c serial interface and is capable of operation across a broad voltage range (1.7v to 3.6v). this device is jedec jc42.4 (ee1004-v) serial presence detect (spd) compliant and includes reversible software write protection for each of four independent 128 x 8-bit blocks. the device features a page write capability of up to 16 bytes of data. address pins allow up to eight devices on the same bus. the 34aa04 is available in the 8-lead pdip, soic, tssop, tdfn, and udfn packages. package types block diagram part number v cc range max. clock frequency temp ranges 34aa04 1.7-3.6 1 mhz (1) i, e note 1: 400 khz for 1.8v v cc < 2.2v 100 khz for v cc < 1.8v a0a1 a2 v ss 12 3 4 87 6 5 v cc nc scl sda a0 a1 a2 v ss nc scl sda v cc 87 6 5 1 2 3 4 tdfn/udfn pdip/soic/tssop i/o control logic memory control logic xdec hv generator write-protect circuitry ydec v cc v ss sense amp. r/w control sda scl a0 a1 a2 block 0 (000h-07fh) block 1 (080h-0ffh) block 2 (100h-17fh) block 3 (180h-1ffh) 4k i 2 c ? serial eeprom with software write-protect downloaded from: http:///
34aa04 ds20005271b-page 2 ? 2014 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs (except a0) w.r.t. v ss ............................................................................................... -0.3v to 6.5v a0 input w.r.t. v ss ............................................................................................................................... ............ -0.3 to 12v storage temperature............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .....-40c to +125c esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ?????????????????????????????????????????????????? 4kv ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions a bove those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 1-1: dc specifications dc characteristics v cc = +1.7v to +3.6v industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c param. no. symbol characteristic min. max. units conditions a0, a1, a2, scl, and sda d1 v ih high-level input voltage 0.7 v cc v cc + 0.5 v d2 v il low-level input voltage 0.3 v cc 0.2 v cc vv v cc 2.5v v cc < 2.5v d3 v hys hysteresis of schmitt trigger inputs 0.0 v cc v ( note ) d4 v ol low-level output voltage 0.40 0.40 vv i ol = 20.0 ma, v cc = 2.2v i ol = 6.0 ma, v cc = 1.7v d5 v hv high-voltage detect (a0 pin only) 71 0v v cc < 2.2v v cc +4.8 10 v v cc ? 2.2v d6 i li input leakage current 1 ? av in = v ss or v cc d7 i lo output leakage current 1 ? av out = v ss or v cc d8 c in , c out pin capacitance (all inputs/outputs) 1 0p f v cc = 5.5v ( note ) t a = 25c, f clk = 1 mhz d9 i cc write operating current 1.5 ma v cc = 3.6v d10 i cc read 200 ? av cc = 3.6v, scl = 400 khz d11 i ccs standby current 15 ? a ? a industrial automotive sda, scl, v cc = 3.6v a0, a1, a2 = v ss note: this parameter is periodically sampled and not 100% tested. downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 3 34aa04 table 1-2: ac specifications ac characteristics v cc = +1.7v to +3.6v industrial (i): t a = -40c to +85c automotive (e): t a = -40c to +125c param. no. symbol characteristic min. max. units conditions 1f clk clock frequency ( note 2 ) 1010 10 100400 1000 khz 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 2t high clock high time 4000 600260 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 3t low clock low time 4700 1300 500 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 4t r sda and scl rise time ( note 1 ) 1000 300120 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 5t f sda and scl fall time ( note 1 ) 300300 120 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 6t hd : sta start condition hold time 4000 600260 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 7t su : sta start condition setup time 4700 600260 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 8t hd : dat data input hold time 0 ns ( note 3 ) 9t su : dat data input setup time 250 100 50 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 10 t su : sto stop condition setup time 4000 600260 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 11 t aa output valid from clock ( note 3 ) 200200 3450 900350 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 12 t buf bus free time: time the bus must be free before a new transmission can start 47001300 500 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 2.2v 2.2v ? v cc ? 3.6v 13 t sp input filter spike suppression (sda and scl pins) 5 0n s ( note 1 ) 14 t wc write cycle time (byte or page) 5 ms 15 t timeout bus timeout time 25 35 ms 16 endurance 1m cycles page mode, 25c, v cc = 3.6v ( note 4 ) note 1: not 100% tested. 2: the minimum clock frequency of 10 khz is to prevent the bus timeout from occurring. 3: as a transmitter, the device must provide an internal mi nimum delay time to bridge the undefined region (minimum 200 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchips web site at www.microchip.com. downloaded from: http:///
34aa04 ds20005271b-page 4 ? 2014 microchip technology inc. figure 1-1: bus timing data scl sda in sda out 5 7 6 13 3 2 89 11 d3 4 10 12 downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 5 34aa04 2.0 pin descriptions the descriptions of the pins are listed in tab l e 2 - 1 . table 2-1: pin function table 2.1 a0, a1, a2 chip address inputs the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight 34aa04 devices may be connected to the same bus by using different chip select bit combina- tions. these inputs must be connected to either v ss or v cc . the a0 pin also serves as the high-voltage input for enabling the swpn and cwp instructions. 2.2 serial address/data input/output (sda) this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal. therefore, the sda bus requires a pull- up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400khz and 1mhz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.3 serial clock (scl) this input is used to synchronize the data transfer to and from the device. symbol pdip soic tssop udfn tdfn description a0/v hv 1 1 1 1 1 chip address input, high-voltage input a1 2 2 2 2 2 chip address input a2 3 3 3 3 3 chip address input v ss 4 4 4 4 4 ground sda 5 5 5 5 5 serial address/data i/o scl 6 6 6 6 6 serial clock nc 7 7 7 7 7 not connected v cc 8 8 8 8 8 +1.7v to 3.6v power supply note: exposed pad on tdfn/udfn can be connected to v ss or left floating. note: the comparison between the a0, a1, and a2 pins and the corresponding chip select bits is disabled for software write- protect and bank select commands. downloaded from: http:///
34aa04 ds20005271b-page 6 ? 2014 microchip technology inc. 3.0 functional description the 34aa04 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data, as a receiver. the bus has to be controlled by a master device, which generates the serial clock (scl), controls the bus access and gener- ates the start and stop conditions, while the 34aa04 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. the 4 kbit array of the 34aa04 is divided into two separate banks of 2 kbits each. the 34aa04 also offers reversible software write protection for each of four 1 kbit blocks. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined ( figure 4-1 ). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is determined by the master device and is, theoretically, unlimited; although only the last sixteen will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first-in, first-out (fifo) fashion. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. exceptions to this rule relating to software write protection are described in section 9.0 ?software write protection? . the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end-of- data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (34aa04) will leave the data line high to enable the master to generate the stop condition. 4.6 bus timeout if scl remains low for the time specified by t timeout , the 34aa04 will reset the serial interface and ignore all further communication until another start condition is detected ( figure 4-2 ). this dictates the minimum clock speed as defined by f clk . note: the 34aa04 does not generate any acknowledge bits if an internal programming cycle is in progress. downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 7 34aa04 figure 4-1: data transfer sequence on the serial bus figure 4-2: bus timeout 4.7 device addressing a control byte is the first byte received following the start condition from the master device. the first part of the control byte consists of a 4-bit control code which is set to 1010 for normal read and write operations and 0110 for accessing the software write-protect features and bank selection. the control byte is followed by three chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 34aa04 devices on the same bus and are used to determine which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. the eighth bit of slave address determines if the master device wants to read or write to the 34aa04 ( figure 4-3 ). when set to a one, a read operation is selected. when set to a zero, a write operation is selected. figure 4-3: control byte allocation scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition scl t timeout ( min )t timeout ( max ) t low < t timeout ( min ): bus interface does not reset. t timeout ( min ) < t low < t timeout ( max ): bus interface may or may not reset. t timeout ( max ) < t low : bus interface will reset. operation control code chip select r/w read 1010 a2 a1 a0 1 write 1010 a2 a1 a0 0 read write-protect/ bank address 0110 a2 a1 a0 1 set write-protect/ bank address 0110 a2 a1 a0 0 or start read/write slave address r/w a 1 0 1 0 a2 a1 a0 0 1 1 0 a2 a1 a0 downloaded from: http:///
34aa04 ds20005271b-page 8 ? 2014 microchip technology inc. 5.0 bank addressing to support backwards-compatibility with ddr2/3 (jedec ee1002) spd eeproms, the memory array of the 34aa04 is divided into two separate 256-byte banks. the set bank address (sba) commands are used to set the bank address to either 0 or 1 . the read bank address (rba) command is used to determine which bank is currently selected. table 5-1: bank address range table 5-2: bank addressing instruction set 5.1 set bank address (sba) the set bank address (sba) commands are used to select the array bank for future read and write operations. the master generates a start condition followed by the corresponding control byte for the chosen sba command ( table 5-2 ), with the r/w bit set to a logic 0 . note that chip select bit a0 of the control byte effectively determines which bank is selected. the 34aa04 will respond with an acknowledge, and then the master transmits two dummy bytes. the 34aa04 will not acknowledge either dummy byte. finally, the master generates a stop condition to end the operation ( figure 5-1 ). array read and write commands will operate in the newly-selected bank until another sba command is executed, or the 34aa04 experiences a por or bor event. figure 5-1: set bank address note 1: the bank address is volatile and is reset to bank 0 upon power-up. 2: the comparison between the a0, a1, and a2 pins and the corresponding chip select bits is disabled for bank select commands. note: sequential read operations cannot cross a bank boundary and will roll over back to the beginning of the selected bank. bank logical array address bank 0 000h-0ffh bank 1 100h-1ffh function abbr control byte a0 pin control code chip select bits r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set bank address to 0 sba0 0110 11000 , 1 , or v hv set bank address to 1 sba1 11100 , 1 , or v hv read bank address rba 11010 , 1 , or v hv s p bus activity master sda line bus activity st a r t st o p control byte dummy byte a c k 0110 0 dummy byte 11 a 1 0 no a c k no a c k note 1: chip select bit a0 specifies which bank to select. downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 9 34aa04 5.2 read bank address (rba) the read bank address (rba) command allows the 34aa04 to indicate which array bank is currently selected. the master generates a start condition and transmits the rba control byte ( ta b l e 5 - 2 ), with the r/w bit set to logic 1 . if bank 0 is currently selected, the 34aa04 will respond with an acknowledge signal. if bank 1 is currently selected, an acknowledge will not be generated. regardless of the result, the master must read at least one dummy byte from the 34aa04, transmitting a not acknowledge signal after each byte, and generate a stop condition to end the command ( figure 5-2 ). figure 5-2: read bank address sp bus activity master sda line bus activity st o p control byte no a c k st a r t 011 0 1 dummy byte a 1 c k note 1: the 34aa04 will only acknowledge if bank 0 is currently selected. 110 2: in accordance with the jedec spec, the master is allowed to read multiple dummy bytes, transmitting a not acknowledge after each byte. downloaded from: http:///
34aa04 ds20005271b-page 10 ? 2014 microchip technology inc. 6.0 write operations 6.1 byte write following the start signal from the master, the control code (4 bits), the chip select bits (3 bits) and the r/w bit, which is a logic low, are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that the array address byte will follow, once it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the array address and will be written into the address pointer of the 34aa04. after receiving another acknowledge signal from the 34aa04, the master device will transmit the data byte to be written into the addressed memory location. the 34aa04 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, which means that during this time, the 34aa04 will not generate acknowledge signals ( figure 6-1 ). if an attempt is made to write to a software write-pro- tected portion of the array, the 34aa04 will not acknowl- edge the data byte, no data will be written, and the device will immediately accept a new command. 6.2 page write the write control byte, array address and the first data byte are transmitted to the 34aa04 in the same way as in a byte write. instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 34aa04, which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. upon receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the array address, as well as the bank selection, remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an internal write cycle will begin ( figure 6-2 ). if an attempt is made to write to a software write-pro- tected portion of the array, the 34aa04 will not acknowledge the data byte, no data will be written, and the device will immediately accept a new command. table 6-1: device response when writing data figure 6-1: byte write note: it is recommended to perform a set bank address command before initiating a write command to ensure the desired bank is selected. note: when doing a write of less than 16 bytes, the data in the rest of the page is refreshed along with the data bytes being written. this will force the entire page to endure a write cycle. for this reason, endurance is specified per page. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or page size) and end at addresses that are integer mul- tiples of [page size C 1]. if a page write command attempts to write across a phys- ical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is, therefore, necessary for the application software to prevent page write operations that would attempt to cross a page boundary. status command ack address ack data byte ack write cycle protected with swpn page or byte write in protected block ack address ack data noack no not protected page or byte write ack address ack data ack yes s p bus activity master sda line bus activity st a r t st o p control byte array address data ac k ac k ac k downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 11 34aa04 figure 6-2: page write s p bus activity master sda line bus activity st a r t control byte array address (n) data (n) data (n + 15) st o p ac k ac k ac k ac k ac k data (n + 1) downloaded from: http:///
34aa04 ds20005271b-page 12 ? 2014 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for flow diagram. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 13 34aa04 8.0 read operation read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to 1 . there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 34aa04 contains an address counter that maintains the address of the last byte accessed, inter- nally incremented by 1 . therefore, if the previous access (either a read or write operation) was to address n , the next current address read operation would access data from address n+1 . upon receipt of the slave address with r/w bit set to 1 , the 34aa04 issues an acknowledge and transmits the 8-bit data value. the master will not acknowledge the transfer, but does generate a stop condition and the 34aa04 discontinues transmission ( figure 8-1 ). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the array address must first be set. this is done by sending the array address to the 34aa04 as part of a write operation. once the array address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a 1 . the 34aa04 then issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 34aa04 discontinues transmission ( figure 8-2 ). 8.3 sequential read sequential reads are initiated in the same way as a random read, with the exception that after the 34aa04 transmits the first data byte, the master issues an acknowledge, as opposed to a stop condition in a random read. this directs the 34aa04 to transmit the next sequentially addressed 8-bit word ( figure 8-3 ). to provide sequential reads, the 34aa04 contains an internal address pointer, which is incremented by one at the completion of each operation. sequential reads are limited to a single bank per operation, so the address pointer allows the entire memory contents of the current bank to be serially read during one opera- tion. 8.4 noise protection and brown-out the 34aa04 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.35v at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. figure 8-1: current address read note: it is recommended to perform a set bank address command before initiating a read command to ensure the desired bank is selected. sp bus activity master sda line bus activity st o p control byte data (n) ac k no a c k st a r t downloaded from: http:///
34aa04 ds20005271b-page 14 ? 2014 microchip technology inc. figure 8-2: random read figure 8-3: sequential read s p s bus activity master sda line bus activity st a r t st o p control byte ac k array address (n) control byte st a r t data (n) ac k ac k n o a c k p bus activity master sda line bus activity st o p control byte ac k n o a c k data (n) data (n + 1) data (n + 2) data (n + x) ac k ac k ac k downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 15 34aa04 9.0 software write protection the 34aa04 has a reversible software write-protect feature that allows each of four 128-byte blocks to be individually write-protected. the write protection is set by executing the set write protect (swpn) commands. the clear all write protect (cwp) command is used to unprotect all of the blocks at once. it is not possible to unprotect blocks individually. the read protection status (rps) commands are used to determine if a given block is currently write- protected. the 34aa04 will not respond with an acknowledge following the data bytes of write operations that are attempted within a write-protected block. table 9-1: block address range table 9-2: software write protection instruction set 9.1 set write protection (swpn) the set write protection (swp) commands are used to set the reversible write protection for individual array blocks. there are four different swp commands, one for each block. v hv must be applied to the a0 pin for the entire swp command. then, the command is executed in a manner similar to an array byte write command. following the start condition, the 0110 control code and the three chip select bits that correspond to the desired swp command ( ta bl e 9 - 2 ) are transmitted by the master, along with the r/w bit as a logic 0 . after the 34aa04 responds with an acknowledge, the master transmits two dummy bytes, after each of which the 34aa04 responds with an acknowledge. finally, the master generates a stop condition, which initiates the internal write cycle and, during this time, the 34aa04 will not generate acknowledge signals ( figure 9-1 ). if the specified block is already write-protected, the swp command is ignored, no acknowledges will be sent, and the internal write cycle will not be executed. note: the write-protect state of each block is stored in nonvolatile bits. block logical array address block 0 000h - 07fh block 1 080h - 0ffh block 2 100h - 17fh block 3 180h - 1ffh note: the comparison between the a0, a1, and a2 pins and the corresponding chip select bits is disabled for software write- protect commands. function abbr control byte a0 pin control code chip select bits r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set write protection, block 0 swp0 0110 0010 v hv set write protection, block 1 swp1 1000 v hv set write protection, block 2 swp2 1010 v hv set write protection, block 3 swp3 0000 v hv clear all write protection cwp 0110 v hv read protection status, block 0 rps0 00110 , 1 , or v hv read protection status, block 1 rps1 10010 , 1 , or v hv read protection status, block 2 rps2 10110 , 1 , or v hv read protection status, block 3 rps3 00010 , 1 , or v hv downloaded from: http:///
34aa04 ds20005271b-page 16 ? 2014 microchip technology inc. figure 9-1: set write protection table 9-3: device response when defining write protection 9.2 clear all write protection (cwp) the clear all write protection (cwp) command resets all of the write protection in a single operation. it is executed in the same manner as a swp command, except using the cwp control byte ( ta bl e 9 - 2 ). the 34aa04 will always acknowledge and execute a cwp command if an internal write cycle is not in progress, regardless of the state of write protection. 9.3 read protection status (rps) the read protection status (rps) commands provide a way of determining whether or not the specified block is currently write-protected. following the start condition, the master transmits the control byte for the desired rps command ( tab le 9 - 2 ), with the r/w bit set to logic 1 . if the specified block is not write-protected, the 34aa04 will respond with an acknowledge signal. if the block is currently write- protected, an acknowledge will not be generated. regardless of the result, the master must read at least one dummy byte from the 34aa04, transmitting a not acknowledge signal after each byte, and generate a stop condition to end the command ( figure 9-3 ). figure 9-2: clear all write protection status command ack address ack data byte ack write cycle protected with swpn swpn noack dont care noack dont care noack no cwp ack dont care ack dont care ack yes not protected swpn or cwp ack dont care ack dont care ack yes a 2 c k s p bus activity master sda line bus activity st a r t st o p control byte dummy byte a 2 c k 0110 a 1 0 2 a 1 1 a 1 0 note 1: chip select bits a0-a2 vary depending on which swp command is being executed. dummy byte a 2 c k 2: the 34aa04 will only acknowledge if the specified block is not currently write-protected. a0 pin v hv a c k s p bus activity master sda line bus activity st a r t st o p control byte dummy byte a c k 0110 0 dummy byte a c k 011 a0 pin v hv downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 17 34aa04 figure 9-3: read protection status table 9-4: device response when reading write protection status status command ack data byte ack protected with swpn rpsn noack dont care noack not protected rpsn ack dont care noack sp bus activity master sda line bus activity st o p control byte no a c k st a r t 011 0 1 a 1 0 dummy byte a 1 2 a 1 1 a 2 c k note 1: chip select bits a0-a2 vary depending on which rps command is being performed. 2: the 34aa04 will only acknowledge if the specified block is not currently write-protected. 3: in accordance with the jedec spec, the master is allowed to read multiple dummy bytes, transmitting a not acknowledge after each byte. downloaded from: http:///
34aa04 ds20005271b-page 18 ? 2014 microchip technology inc. 10.0 packaging information 10.1 package marking information xxxxxxxxxxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (3.90 mm) example: xxxxxxxx xxxxyyww nnn 34aa04 3 ec 1442 34aa04 1442 3ec 8-lead tssop example: xxxx yyww nnn aack 1442 3ec 8-lead 2x3 tdfn xxx yww nn example: 3 e 3 e acb 442 3e 1st line marking codes part number pdip soic tssop tdfn udfn 34aa04 34aa04 34aa04 aack acb cac 8-lead 2x3 udfn xxx yww nn example: cac 442 3e downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 19 34aa04 legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) jedec ? designator for matte tin (sn) note : for very small packages with no room for the jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e * standard otp marking consists of microchip part number, year code, week code, and traceability code. downloaded from: http:///
34aa04 ds20005271b-page 20 ? 2014 microchip technology inc. b a for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing no. c04-018d sheet 1 of 2 8-lead plastic dual in-line (p) - 300 mil body [pdip] eb e a a1 a2 l 8x b 8x b1 d e1 c c plane .010 c 12 n note 1 top view end view side view e downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 21 34aa04 microchip technology drawing no. c04-018d sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 8-lead plastic dual in-line (p) - 300 mil body [pdip] units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a - - .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb - - .430 bsc: basic dimension. theoretically exact value shown without tolerances. 3. 1. protrusions shall not exceed .010" per side. 2.4. noes: -- dimensions d and e1 do not include mold flash or protrusions. mold flash or pin 1 visual index feature may vary, but must be located within the hatched area. significant characteristic dimensioning and tolerancing per asme y14.5m e datum a datum a e b e 2 b e 2 alternate lead design (vendor dependent) downloaded from: http:///
34aa04 ds20005271b-page 22 ? 2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 23 34aa04 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
34aa04 ds20005271b-page 24 ? 2014 microchip technology inc. downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 25 34aa04 d n e e1 note 1 12 b e c a a1 a2 l1 l downloaded from: http:///
34aa04 ds20005271b-page 26 ? 2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 27 34aa04 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
34aa04 ds20005271b-page 28 ? 2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 29 34aa04 downloaded from: http:///
34aa04 ds20005271b-page 30 ? 2014 microchip technology inc. downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 31 34aa04 downloaded from: http:///
34aa04 ds20005271b-page 32 ? 2014 microchip technology inc. appendix a: revision history revision b (10/2014) removed preliminary condition. updated section 10.0, packaging information . minor typographical corrections. revision a (03/2014) original release of this document. downloaded from: http:///
? 2014 microchip technology inc. ds20005217b-page 33 34aa04 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: product support C data sheets and errata, appli- cation notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on cus- tomer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
34aa04 ds20005271b-page 34 ? 2014 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office. part no. x /xx package temperature range device device: 34aa04: = 1.7v, 4 kbit i 2 c serial eeprom 34aa04t: = 1.7v, 4 kbit i 2 c serial eeprom (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (3.90 mm body), 8-lead st = plastic tssop (4.4 mm), 8-lead mny (1) = plastic dual flat, no lead package (2x3x0.75 mm body), 8-lead muy (1) = plastic dual flat, no lead package (2x3x0.5 mm body), 8-lead examples: a) 34aa04-i/p: industrial temperature, 1.7v, pdip package b) 34aa04-i/sn: industrial temperature, 1.7v, soic package c) 34aa04t-e/muy: tape and reel, automotive temperature, 1.7v, udfn package d) 34aa04t-i/mny: tape and reel, indus- trial temperature, 1.7v, tdfn package e) 34aa04-e/st: automotive temperature, 1.7v, tssop package note 1: y indicates a nickel palladium gold (nipdau) finish. C downloaded from: http:///
? 2014 microchip technology inc. ds20005271b-page 35 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-747-9 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
ds20005271b-page 36 ? 2014 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7830 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 germany - pforzheim tel: 49-7231-424750 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 03/25/14 downloaded from: http:///

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